Novinka:NXP: ARM® Cortex™-M3 - LPC1800
(Kategória: Semiconductor-ZONE)
Zaslal EdizonTN
20.09.2010-11:13

Spoločnosť NXP predstavila na priebiehajúcom podujatí ESC Boston 2010, novú radu ARM CORTEX-M3 mikrokontrolérov - LPC1800.

Vlastnosti
  • Processor core
    • ARM Cortex-M3 processor, running at frequencies of up to 150 MHz.
    • ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
    • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
    • Non-maskable Interrupt (NMI) input.
    • JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
    • ETM and ETB support.
    • System tick timer.

  • On-chip memory
    • 136 kB SRAM for code and data use.
    • Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually.
    • 32 kB ROM containing boot code and on-chip software drivers.
    • 32-bit One-Time Programmable (OTP) memory for customer use.

  • Clock generation unit
    • Crystal oscillator with an operating range of 1 MHz to 25 MHz.
    • 12 MHz internal RC oscillator trimmed to 1% accuracy.
    • Ultra-low power RTC crystal oscillator.
    • Two PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. Second PLL can be used for USB.
    • Clock output.

  • Serial interfaces:
    • Quad SPI Flash Interface (SPIFI) with four lanes and up to 80 Mbps/lane.
    • 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load.
    • One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip PHY.
    • One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.
    • Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support synchronous mode and a smart
      card interface conforming to ISO7816 specification.
    • One C_CAN 2.0B controller with one channel.
    • Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
    • One Fast-mode Plus I2C- bus interface with monitor mode and with open- drain I/O pins conforming to the full I2C- bus specification. Supports data rates of up to
      1 Mbit/s.
    • One Fast-mode Plus I2C- bus interfaces with monitor mode and standard I/O pins supporting data rates of up to 1 Mbit/s.
    • One I2S interface with DMA support and with one input and one output.

  • Digital peripherals:
    • External Memory Controller (EMC) supporting external SRAM, ROM, flash, and SDRAM devices.
    • LCD controller with DMA support and a programmable display resolution of up to 1024H × 768V. Supports monochrome and color STN panels and TNT color
      panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.
    • SD card interface.
    • Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB slaves.
    • Up to 80 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open- drain modes.
    • GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
    • State Configuration Timer (SCT) subsystem on AHB.
    • Four general-purpose timer/counters with capture and match capabilities.
    • One motor control PWM for three-phase motor control.
    • One Quadrature Encoder Interface (QEI).
    • Repetitive Interrupt timer (RI timer).
    • Windowed watchdog timer.
    • Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
    • Alarm timer; can be battery powered.

  • Analog peripherals:
    • One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
    • Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.

  • Security:
    • AES decryption engine.
    • Two 128-bit secure OTP memories for AES key storage and customer use.
    • Unique Id for each device.

  • Power:
    • Single 3.3 V (2.0 V to 3.6 V) power supply with on-chip DC-DC converter for the core supply and the RTC power domain.
    • RTC power domain can be powered separately by a 3 V battery supply.
    • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
    • Overdrive mode to increase CPU and bus clock frequency.
    • Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.
    • Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC
      power domain.
    • Brownout detect with four separate thresholds for interrupt and forced reset.
    • Power-On Reset (POR).

  • Available as 100-pin and 144-pin LQFP packages and as 180-pin and 256-pin LBGA packages.



Blokové zapojenie


Cena
Momentálne sú dostupné len vzorky.

Odkazy
LPC18xx series device Homepage
LPC18x0 Datasheet


Distribúcia
viď. Adresár

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